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doc. version : 5 total pages : 20 date : 200 2 . 12 . 09 note: the content of this specification is subject to change. ? 2002 au optronics all rights reserved, do not copy. model name: a015an02 v1 product specification 1.5 ?a color tft - lcd module < >preliminary specification < ?? > final specification www..net www..net
record of revision version revise date page content 0 20/may./2002 first draft. 1 27/may./2002 15 revised the error 17 revised the error 18 ad d the extraction block of display data 2 31/may/2002 3 surface treatment: hard coating(3h) 7 v cac ,v gl - ac : 5.2v ? 5.6v 8 dc - dc block output voltage: 13v ? 13.5 v; vref: 1.25v ? 1 .2v 12 add fpc reliability test item 13 update outline drawing 21 updated application circuit 3 03/sep/2002 14 change package to 420 pcs/box 4 31/oct/2002 6 vcom from 5.2 to 5.6 7 v gl_h from ? 10 to ? 7.1 8 delete data set - up time and data hold time on table and tc ? tvc 9 delete sel0 sel1 in note fo drawing 18 hsync clk 1560 ? 360 19 modify drawing (pixel arrangment) 5 09/dec/2002 7 remove led typical voltage and add le d maximum voltage www..net www..net
version : 2 page : 1 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. contents: a. physical specification ..................................................... p3 b. electrical specifications ................................................... p4 1. pin assignmen t ............................................................ p4 a. t ft - lcd panel driving section ........................................... p5 b. backlight driving section ................................................. p5 2. equivalent circuit of i/o ............................................... p6 3. absolute maximum ratings .................................................. p6 4. electrical characteristics .................................................... p7 a. typical operating conditions ............................................. p7 b. current consumption ..... ............................................... p7 c. backlight driving conditions ......................................... p7 5. ac timing ................................................................. p7 a. timing conditions ......................... .............................. p7 b. timing diagram ......................................................... p8 6. dc - dc converter circuit ................................................. p9 a. boost converter ...................................... ................. p9 b. shutdown mode ...................................................... p10 c. oscillator circuit ...................................................... p10 www..net www..net
version : 2 page : 2 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. c. optical specifications ............................................ ......... p11 d. reliability test items ....................................................... p12 e. packing form ............................................................... p14 appendix: fig1 dc - dc converter block diagram .......................... .............. p9 fig2 dcck block diagram .................................................... p10 fig3.pwm control state diagram ............................................. p10 fig.4 outline dimension of tft - lcd module .................................. ..... p15 fig.5 input signal timing relationship ? . ........................................... p16 fig.6 input vertical timing ....................................................... p17 fig.7 horizontal input timing ..................................... ............... p18 fig.8 extraction of display data from memory to panel ............................... p19 fig.9 hsync,vsync,data,dclk relationship .............................. p20 fig.10 application circuit ........................................... ......... p21 www..net www..net
version : 2 page : 3 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. a. physical specifications no. item specification remark 1 display resolution(dot) 280(w) ?? 2 20 (h) 2 active area(mm) 29.54(w) ?? 22.22(h) 3 screen size(inch) 1.45(diagonal) 4 dot pitch(mm) 0.1055(w) ?? 0.101(h) 5 co lor configuration r. g. b. delta 6 overall dimension(mm) 40.5(w) ?? 34.65(h) ?? 3.9 ( d) note 1 7 weight(g) 10 + 2 8 panel surface treatment hard coating (3h) note 1: refer to fig. 4 www..net www..net
version : 2 page : 4 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. b. electrical specifications 1.pin assignme nt a. tft - lcd panel driving section pin no symbol i/o description remark 1 gnd - ground for gate 2 v cc p supply voltage of logic control circuit for scan driver 3 v gl p negative power for scan driver 4 v gh p positive power for scan driver 5 frp o gate driver input signal that is frame polarity output for vcom 6 vcom i common electrode driving signal 7 drv vo power transistor gate signal for the boost converter 8 agnd - ground pins for analog circuits 9 fb vi main boost regulator feedback input(fb threshold is 1.2v) 10 shl i left/right scan control input note 1 11 stb i stand by mode setting pin. note 2 12 v cc p supply voltage for source driver 13 shdb i shutdown input. active low. note 3 14 agnd p ground pins for analog circuits 1 5 vled i led anode 16 gled o led cathode 17 avdd p power supply for analog circuits 18 hsync i horizontal sync input. negative polarity 19 vsync i vertical sync input. negative polarity. 20 dclk i clock signal; latch data onto line latches at the rising edge. 21 d07 i data input. :msb 22 d06 i data input 23 d05 i data input 24 d04 i data input 25 d03 i data input 26 d02 i data input. :lsb 27 sel0 i select pin for interface definition note 4 www..net www..net
version : 2 page : 5 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. 28 grb i global reset pin. note 5 29 u/d i up/down scan control input note 1 30 gnd - gnd for logic circuit 31 avdd1 p supply of positive power for level shift circuit. 32 agnd1 p ground for level shift circuit i: input; o: output. vi: voltage input vo: voltage output p:power note 1: selection of scanning mode mode setting of scan control input scanning direction u/d shl note 5 normal mode l h from up to down, and from left to right. reverse mode h l from down to up, and from right to left. note 2: stand by mode(stb).if stb high , it is normal operation. if it is low, it is standby function. normally pulled high. note 3:shutdown input(shdb).active low, dc - dc converter is off when shdb is low, normally pulled low. note 4: interface select pin, pull low for ups051 interf ace note 5:global reset pin. it should be connected to vcc in normal operation. if connected to gnd, the controller is in reset state, normally pulled high. note 5 : definition of scanning direction. refer to figure as below: b. le d driving section no. symbol i/o description remark pin15 vled i led anode pin 16 gled - led cathode www..net www..net
version : 2 page : 6 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. 2. equivalent circuit of i/o pin no & pin name schematics 7.drv 9.fb 10 shl 11.stb 13.shd b 18.hsync 19.vsync 20.dclk 21.d07 22.d06 23.d05 24.d04 25.d03 26.d02 28.grb 29.u/d 3. absolute maximum ratings item symbol condition min. max. unit remark v cc gnd=0 - 0.5 5. v av dd av ss =0 - 0.5 5.5 v v gh - 0.3 21 v v gl gnd=0 - 17 0.3 v power voltage v gh ?e v gl - 38 v input signal voltage vcom - 2.9 5. 6 v operating temperature topa 0 60 j ambient temperature storage temperature tstg - 25 80 j ambient temperature 4. electrical characteristics a. typical operating conditions (gnd=avss=0v) item symbol min. typ. max. unit remark v cc 2.5 3.3 3.6 v av dd 3.2 3.3 4.5 v v cc i i v cc 180? www..net www..net
version : 2 page : 7 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. v gh 15.8 17.8 19.5 v v gl ac - 5.6 - vp - p ac component of v gl. note 1 v gl_h - 8.1 - 7.1 - 6.1 v high level of v gl. v cac - 5.6 - vp - p ac c omponent, note 2 vcom v cdc - 0.4 - 0.1 0.2 v dc component, note 3 note 4 h level v oh vcc - 0.4 output signal voltage l level v ol gnd gnd+0.4 h level v ih 0.7v cc - v cc v input signal voltage l level v il gnd - 0.3v cc v drv output voltage v drv 0 vcc v drv output current idrv 10 ma feedback voltage v fb 1.2 1.25 v for dc/dc circuits. h level ioh 10 ua output current l level iol - 10 ua analog stand by current ist 200 ua dclk is stopped h level i ohf 20 ma frp output current l level i olf 20 ma for vcom circuits. note 1: the same phase and amplitude with common electrode driving signal (vcom). note 2: the brightness of lcd panel could be adjusted by the adjustment of the ac component of vcom. note 3: v cdc could be adjusted so as to minimize vertical straight line, flicker and maximum contrast on each module. note 4: be sure to apply gnd, v cc and v gl (v gl must lower than 0 volt) to the lcd first, and then apply v gh . note 5: the applicable pins are shl,stb,shdb,hsync,vsync,dclk,d05~d0 0,grb,u/d b. current consumption (gnd=avss=0v) parameter symbol condition min. typ. max. unit remark i gh v gh =17v - 0.13 0.8 m a i gl v gl _ h = - 7.1 v - - 0.19 - 1 m a i cc v cc =3.3v - 2 4 m a current for driver i dd av dd =3.3v - 1.15 2 m a c. led driving co nditions parameter symbol min. typ. max. unit remark led current 20 ma led voltage v l 8 v led life time l l 10000 hr note 1,2 note 1 : ta. = 25 j , i l = 20ma www..net www..net
version : 2 page : 8 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. note 2 : brightness to be decreased to 50% of the initial value. 5. ac timing a. ti ming conditions parameter symbol min. typ. max. unit. remark frequency 1/tvc 5.67 mhz high time tvch 15 ns dclk low time tvcl 15 ns rising time t r - - 10 ns note 1 falling time t f - - 10 ns note 1 60 63.56 67 us period th 360 dclk display period thd 49.4 us pulse width thp 1 25 dclk hsync hsync - clk timing thc 15 t v c - 15 ns note 2 hsync setup time tvst 12 ns hsync hold time thhd 12 ns horizontal lines per field t v 256 262 268 t h 16.6 ms period tv 262 t h display period tvd 13.97 ms 1 dclk vsync pulse width tvp 3 th note 2 vsync setup time tvst 12 ns vsync hold time tvhd 12 ns dclk - data timing tds 10 - - ns data - clk timin g tdh 10 - - ns data d00~d05 rising time falling time tdrf - - 10 ns note 1: for all of the logic signals. note 2: display position a. . horizontal display position the display starts from the data of (57dclk, the=57dclk) as shown in fig 5. ( the : from hsync falling edge to 1 st displayed data.) b. vertical display position parameter symbol min. typ. max. unit remark vertical display position tvs 25 th ntsc b. timing diagram www..net www..net
version : 2 page : 9 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. please refer to the attached drawing, from fig.5 to fig.8. 6. dc - dc converter circuit a015an02 v1 c ontains one high - power step - up dc - dc converter, and backplane drive circuitry for active matrix tft lcds. the output voltage of the main boost converter can be set from vcc to 13.5v with external resistors. also included in a015an02 v1 are a precision 1.2v reference voltage, fault detection and logic shutdown. a .boost converter a015an02 v1 main boost converter uses a boost pwm architecture to produce a positive regulated voltage, please refer to the below figures to see the block diagram. fig 1 dc - dc converter block diagram in the internal architecture of dc - dc converter. the feedback voltage(vfb) will connect to the tri - angle waveform comparator ,and generates the output signal (cp0) which determines the duty cycle for ( fdc). fig 2 dcck block diagram www..net www..net
version : 2 page : 10 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. to reduce the noise affect,cp0 will processed by de - bounce circuit. state - machine will generate the duty cycle by cp0 signal. to make sure that vfb can reach default vref quickly, so state - m achine?s is designed as a discrete step by step function. please refer to fig 3. if cp0 is low , duty cycle will work from 0% to 75%. the maximum duty ratio is 75%. fig 3 pwm control state diagram b.shutdown mode in shutdown mode, a logic - low level on shdb, pwm controller and the reference are disabled. the supply current drops to maximize battery life and the reference is pulled to ground. every output voltage will decay. if unused, connect shdb to vcc. c.oscillator circuit the boost - converter operating frequency was set at 1/16 times the system clock, dclk. in a015an02 v1 ?s model. the dc - dc converter osc frequency is dclk/16=354.4khz c. optical specification (note 1,note 2, note 3 ) item symbol condition min. typ. max . unit remark response time rise fall tr tf c =0 x - - 25 30 50 60 ms ms note 4 contrast ratio cr at optimized v i ewing angle 60 150 - note 5,6 www..net www..net
version : 2 page : 11 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. viewing angle top bottom left right cr ? 10 10 30 45 45 - - - - - - - - deg . note 7 brightness y l c =0 x 160 (200) - cd/m 2 note 8 x c =0 x (0.26) (0.31) (0.36) white chromaticity y c =0 x (0.29) (0.35) (0.40) note 1. ambient temperature =25 j . and backlight current i l =20 ma note 2. to be measured in the dark room. note 3.to be measured on the center ar ea of panel with a field angle of 1 x by topcon luminance meter bm - 7, after 10 minutes operation. note 4. definition of response time: the output signals of photo detector are measured when the input signals are changed from ?black? to ?white?(falling time) and from ?white? to ?black?(rising time), respectively. the response time is defined as the time interval between the 10% and 90% of amplitudes. refer to figure as below. note 5. definition of contrast ratio: contrast ratio is calculated with the follo wing formula. photo detector output when lcd is at ?white? state photo detector output when lcd is at ?black? state note 6. white vi=v i50 ?? 1.5v black vi=v i50 ? 2.0v ? ? ? means that the analog input signal swings i n phase with com signal. ? ? means that the analog input signal swings out of phase with com signal. v i50 : the analog input voltage when transmission is 50% the 100% transmission is defined as the transmission of lcd panel when all the input terminals of module are electrically opened. note 7. definition of viewing angle: refer to figure as below. signal(relative value) "black" tr tf "white" "white" 0 % 10 % 90 % 100 % contrast ratio (cr)= www..net www..net
version : 2 page : 12 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. note 8. measured at the center area of the panel when all the input terminals of lcd panel are electrically opened. d. reliability test items: no. test items conditions remark 1 high temperature storage ta= 80 j 240h rs 2 low temperature storage ta= - 2 5 j 240h rs 3 high temperature operation ta= 60 j 240h rs 4 low temperature operation ta= 0 j 240h rs 5 high temperature and high humidity ta= 60 j . 9 0 % rh 240h rs operation 6 heat shock - 2 5 j ~ 80 j /50 cycle 2hrs/cycle non - operation 7 electrostatic discharge ? 200v,200pf(0 [ ) , once for each terminal non - operation frequency range : 10~55hz st oke : 1.5mm sweep : 10~55hz~10hz 2 hours for each direction of x,y,z 8 vibration (6 hours for total) non - operation jis c7021, a - 10 condition a 9 mechanical shock 100 g . 6ms, ? x, ? y, ? z 3 times for each direction non - operation jis c7021, a - 7 condition c 10 vibration (with carton) random vibration: 0.015g 2 /hz from 5~200hz ? 6db/octave from 200~500hz iec 68 - 34 11 drop (with carton) height: 60cm 1 corner, 3 edges, 6 surfaces 12 the copper?s strength for fpc the strength is larger 0.7 kg/cm ipc tm650 13 the film?s strength for fpc the strength is la rger 0.35 kg/cm ipc tm650 www..net www..net
version : 2 page : 13 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. 14 flexible ability for fpc 1. curved radius: 2mm 2. curved angle: 270 3. pulling force: 500g mit folm : diagram of test set up for folding endurance note: ta: ambient temperature. www..net www..net
version : 2 page : 14 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. e. packing form |???ktapy ?a180???| epe(btm cover) epp(after) epp(right) epp(front) www..net www..net
version : 2 page : 15 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. au fig.4 outline dimension of tft - lcd module www..net www..net
version : 2 page : 16 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. fig. 5 input signals timing relationship r1 g2 b3 r4 g5 b6 r7 g8 b9 r10 g11 b12 r13 g14 b15 r16 g17 b18 odd line d0 [ 0 ?g 6 ] dclk hsync vsync ? r19 g20 b21 g1 b2 r3 g4 b5 r6 g7 b8 r9 g10 b11 r12 g13 b14 r15 g16 b17 r18 even line d0 [ 0 ?g 6 ] g19 b20 r21 www..net www..net
version : 2 page : 17 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. vertical invalid data period dh2 dh1 dhn - 1 dhn vertical invalid data period number of v - data line 1 2 3 28 number of line tvs tv d 0.7vcc 0.3vcc tvp tv vertical sync. signal ( vsync) horizontal sync. signal (hsync) dot signal (r0 - r5,g0 - g5, b0 - b5) fig .6 input vertical timing ? ? ? ? ? ? 90% 90% 10% 10% tr tf www..net www..net
version : 2 page : 18 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. fig. 7 horizontal input timing) invalid data period invalid data period d1 d2 d280 thd number of dot data r1 g2 b3 r4 g5 b6 r7 g8 tdh tds tvcl tvch tvc =1/ dclk thp thc hsync dclk odd linedata signal d0[0,5] dclk d0 [0:5] 0.9vcc 0.1vcc tdrf lcd valid data(280) ? ? ? ? ? 3 60 dclk [ th ] the b9 even linedata signal d0[0,5] g1 b2 r3 g4 b5 r6 g7 b8 ? ? r9 www..net www..net
version : 2 page : 19 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. r1 g2 b3 r4 b6 g5 ?? r280 g1 b2 r3 g4 r6 b5 g 2 80 ? r1 g2 b3 r4 b6 g5 ?? r280 fig.8 extraction of display data from memory to panel www..net www..net
version : 2 page : 20 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. fig. 9 hsync,vsync,data,dclk relationship www..net www..net
version : 2 page : 21 / 21 all rights strictly reserved. any portion of this prper shall not be reproduced, copie d, or transformed to any other forms without permission from au optronics corp. application circuit r110 22k sel0 avdd c104 1uf r101 12k dd3 vgl c113 0.1uf dd3b q100 fmmt619 r114 13k r124 000f led1 nscw215 r127 000f vsyncb c106 0.1uf r103 20k c1 560p c103 1uf dd6b agnd1 l102 22uh c105 10uf dd3b avdd1 r119 000f fb dd7 r120 000f r107 100k c108 0.1uf gnd stb vcc vgl dd5 drv c109 10uf q102 2sd1119 c100 0.1uf shl - r121 000f dd6 r105 30f shl shdb q101 fmmt619 agnd r106 10k stbb hsyncb frp c107 0.1uf grb r128 000f r113 000f ck_out vcc r100 1.3k dd2b avdd1 c116 270p com hsync drv d103 dan217u 1 2 3 1 2 3 l100 22uh 3.3v frp avdd c111 10uf vr100 2k r108 100k vglc dd5b shdb r109 100 dd4b dd5b c101 0.1uf c112 0.1uf dd7b avdd dd4b dd2 vglc r123 000f dd7b vr101 203 1 3 2 vcc com vglc u3 conn32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 stbb r104 2.4k vsync c125 10uf ledvcc dd6b r111 open ledgnd ledvcc vgh c102 0.1uf vsyncb vcc com hsyncb vr103 200k r125 000f r112 10k dd2b u/d vcc dd4 r102 open d102 dan217u 1 2 3 1 2 3 sw vgh ck_out dclk fb r126 000f vr102 50k 1 3 2 grb +9v ledgnd r122 000f c110 1uf d101 ma158 u/d + led2 nscw215 d100 sb07-03c agnd1 fig. 10 typical application circuit (for reference) www..net www..net

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